library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use ieee.numeric_std.all;


entity sound_module_tb is
end sound_module_tb;


architecture TESTBENCH of sound_module_tb is

	component sound_module is
		port (clk, reset: in std_logic;
		enable: in std_logic;
		freqdiv: in std_logic_vector (31 downto 0);
		audio_l, audio_r: out std_logic
		);
	end component;

	for IMPL: SOUND_MODULE use entity WORK.SOUND_MODULE(RTL);

	-- Clock period
	constant period: time := 16 ns;


	signal clk, reset, enable, audio_l, audio_r: std_logic;
	signal freqdiv: std_logic_vector (31 downto 0);
	

begin

	IMPL: SOUND_MODULE port map (clk => clk, reset => reset, enable => enable, audio_l => audio_l, audio_r => audio_r, freqdiv => freqdiv);

	process
	 variable ton1: integer;
	 variable ton2: integer;
	procedure run_cycle is
	    begin
	      clk <= '0';
	      wait for period / 2;
	      clk <= '1';
	      wait for period / 2;
	end procedure;

	begin
		-- Configuration	
		freqdiv <= conv_std_logic_vector (71023, 32);	-- 440 Hz -> 71023
		enable <= '1';
		reset <= '1';
		ton1 := 71023;
		ton2 := 2 * ton1;

		for n in 1 to 5 loop
			run_cycle;
		end loop;

		reset <= '0';
		
		assert false report "Ton1" severity note;
		for n in 1 to ( ton1 * 10 ) loop
			run_cycle;
		end loop;
		
		freqdiv <= conv_std_logic_vector (ton2, 32);
		assert false report "Ton2" severity note;
		for n in 1 to ( ton2 * 5 ) loop
			run_cycle;
		end loop;

		-- End		
		enable <= '0';
		for n in 1 to 5 loop
			run_cycle;
		end loop;

		assert false report "Simulation finished" severity note;
    		wait;
	end process;
end architecture;


